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Disambiguation of "Zyuban, Victor V."

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Runtime power reduction capability of the IBM POWER7+ chip.

, , , , , , , , , and . IBM J. Res. Dev., (2013)

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V Saile

V Geoffroy

V Adams

V Fendrich

V Ustinov

 

Other publications of authors with the same name

Unified architecture level energy-efficiency metric.. ACM Great Lakes Symposium on VLSI, page 24-29. ACM, (2002)Inherently Lower-Power High-Performance Superscalar Architectures., and . IEEE Trans. Computers, 50 (3): 268-285 (2001)Design methodology for semi custom processor cores., , , , , and . ACM Great Lakes Symposium on VLSI, page 448-452. ACM, (2004)A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime., , , and . ISCA, page 353-362. IEEE Computer Society, (2008)Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis., , , , , , , , and . ICCAD, page 458-465. IEEE, (2013)IBM POWER8 circuit design and energy optimization., , , , , , , , , and 13 other author(s). IBM J. Res. Dev., (2015)Optimization of scannable latches for low energy.. IEEE Trans. Very Large Scale Integr. Syst., 11 (5): 778-788 (2003)Optimizing pipelines for power and performance., , , , , , and . MICRO, page 333-344. ACM/IEEE Computer Society, (2002)The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking., , , , , , , , , and 20 other author(s). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)Microarchitectural techniques for power gating of execution units., , , , , and . ISLPED, page 32-37. ACM, (2004)