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Thanks for Nothing: Predicting Zero-Valued Activations with Lightweight Convolutional Neural Networks., , , и . ECCV (10), том 12355 из Lecture Notes in Computer Science, стр. 234-250. Springer, (2020)Task Scheduling Based On Thread Essence and Resource Limitations., , и . J. Comput., 7 (1): 53-64 (2012)Memristor-based IMPLY logic design procedure., , , и . ICCD, стр. 142-147. IEEE Computer Society, (2011)Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors., , и . PAAP, стр. 65-72. IEEE Computer Society, (2010)Non-Blocking Simultaneous Multithreading: Embracing the Resiliency of Deep Neural Networks., и . MICRO, стр. 256-269. IEEE, (2020)Resistive Address Decoder., , и . IEEE Comput. Archit. Lett., 16 (2): 141-144 (2017)Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors., , , , и . IEEE Comput. Archit. Lett., 5 (1): 14-17 (2006)Nahalal: Cache Organization for Chip Multiprocessors., , , и . IEEE Comput. Archit. Lett., 6 (1): 21-24 (2007)Interconnect-power dissipation in a microprocessor., , , и . SLIP, стр. 7-13. ACM, (2004)Multiple clock and voltage domains for chip multi processors., , , и . MICRO, стр. 459-468. ACM, (2009)