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Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique., and . ITC, page 221-229. IEEE Computer Society, (2001)Divide-and-concatenate: an architecture level optimization technique for universal hash functions., , and . DAC, page 614-617. ACM, (2004)Power, Area, Speed, and Security (PASS) Trade-Offs of NIST PQC Signature Candidates Using a C to ASIC Design Flow., , , and . ICCD, page 337-340. IEEE, (2019)Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs., , and . DATE, page 865-869. EDA Consortium, San Jose, CA, USA, (2007)Simulated annealing based yield enhancement of layouts., and . Great Lakes Symposium on VLSI, page 166-169. IEEE, (1994)SLICED: Slide-based Concurrent Error Detection Technique for Symmetric Block Ciphers., , , and . HOST, page 70-75. IEEE Computer Society, (2010)Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors., , and . ISVLSI, page 516-521. IEEE Computer Society, (2014)Optimal Self-Recovering Microarchitecture Synthesis., and . FTCS, page 512-521. IEEE Computer Society, (1993)Hardware security: threat models and metrics., , , and . ICCAD, page 819-823. IEEE, (2013)Memristor based programmable threshold logic array., , , and . NANOARCH, page 5-10. IEEE Computer Society, (2010)