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Hardware transactional memory with software-defined conflicts., , , , , , , and . ACM Trans. Archit. Code Optim., 8 (4): 31:1-31:20 (2012)VAQUERO: A Scratchpad-based Vector Accelerator for Query Processing., , , , , , , and . HPCA, page 1289-1302. IEEE, (2023)VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations., , , , , , , , and . HPCA, page 921-934. IEEE, (2021)Out-of-Order Vector Architectures., , and . MICRO, page 160-170. ACM/IEEE Computer Society, (1997)Fetching instruction streams., , , and . MICRO, page 371-382. ACM/IEEE Computer Society, (2002)Task Superscalar: An Out-of-Order Task Pipeline., , , , , , , and . MICRO, page 89-100. IEEE Computer Society, (2010)Architectural Support for Fair Reader-Writer Locking., , , , , , and . MICRO, page 275-286. IEEE Computer Society, (2010)The impact of traffic aggregation on the memory performance of networking applications., , , and . MEDEA@PACT, page 57-62. ACM, (2004)Evolutionary system for prediction and optimization of hardware architecture performance., , , , , , , and . IEEE Congress on Evolutionary Computation, page 1941-1948. IEEE, (2008)Improved spill code generation for software pipelined loops., , , and . PLDI, page 134-144. ACM, (2000)