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A VLSI architecture for real-time image convolution with large symmetric kernels.

, , , and . ICASSP, page 1961-1964. IEEE, (1988)

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VLSI architectures for dynamic time warping using systolic arrays., , , and . ICASSP, page 778-781. IEEE, (1984)VLSI Architecture for a one chip video median filter., , , and . ICASSP, page 1001-1004. IEEE, (1985)Real-time VLSI architecture for geometric image transformations., , , and . VCIP, volume 1360 of SPIE Proceedings, SPIE, (1990)A single chip VLSI architecture for a real time stereo vision processor., , , and . ICASSP, page 1965-1968. IEEE, (1988)Memory-I/O tradeoff and VLSI implementation of lapped transforms for image processing., and . ICASSP (1), page 393-396. IEEE Computer Society, (1993)A Generalized Precompiling scheme for Surviving Path Memory Management in Viterbi decoders., and . ISCAS, page 1579-1582. IEEE, (1993)A single chip video rate 16×16 discrete cosine transform., , , , and . ICASSP, page 805-808. IEEE, (1986)From image coding to multimedia: Algorithms and architectures for a revolution.. Microprocess. Microprogramming, 35 (1-5): 3 (1992)Optimal VLSI architecture for distributed arithmetic-based algorithms., and . ICASSP (2), page 509-512. IEEE Computer Society, (1994)A Generic Smart Sensor Model for Real-time Distributed Data Acquisition Systems., , , , and . PDPTA, page 329-340. CSREA Press, (1996)