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A novel floating-gate binary signal to multiple-valued signal converter for multiple-valued CMOS logic., , , , and . ICECS, page 579-582. IEEE, (2002)Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers., , , , and . ISCAS (1), page 345-348. IEEE, (2003)Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion., , , and . ISCAS (4), page 838-841. IEEE, (2001)Extreme low-voltage floating-gate CMOS transconductance amplifier., , , , and . ISCAS (1), page 37-40. IEEE, (2001)Novel recharge semi-floating-gate CMOS logic for multiple-valued systems., , , and . ISCAS (5), page 193-196. IEEE, (2003)A 0.3 V floating-gate differential amplifier input stage with tunable gain., , , , and . ICECS, page 413-416. IEEE, (2001)A novel floating-gate multiple-valued signal to binary signal converter., , , and . ICECS, page 575-578. IEEE, (2002)Neuromorphic analog communication., , , and . ICNN, page 920-925. IEEE, (1996)Second order MASH Δ ΣFDM-solution with adaptive improvements., , and . ICECS, page 23-26. IEEE, (2001)A novel floating-gate multiple-valued CMOS full-adder., , , , and . ISCAS (1), page 877-880. IEEE, (2002)