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A Functional-Level Test Generation Methodology Using Two-level Representations.

, and . DAC, page 722-725. ACM Press, (1989)

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Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors., , , and . Digit. Signal Process., 1 (4): 231-244 (1991)Sequential circuit testability enhancement using a nonscan approach., , , and . IEEE Trans. Very Large Scale Integr. Syst., 3 (2): 333-338 (1995)New Techniques for Deterministic Test Pattern Generation., and . J. Electron. Test., 15 (1-2): 63-73 (1999)Efficient Variable Ordering Heuristics for Shared ROBDD., , and . ISCAS, page 1690-1693. IEEE, (1993)Partial Scan Design Based on Circuit State Information., , , and . DAC, page 807-812. ACM Press, (1996)Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists., , , , , and . DAC, page 133-138. ACM Press, (1995)Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator., , and . DAC, page 535-540. IEEE Computer Society Press, (1990)APT: An Area-Performance-Testability Driven Placement Algorithm., , , and . DAC, page 141-146. IEEE Computer Society Press, (1992)Sequential Circuit Test Generation in a Genetic Algorithm Framework., , , and . DAC, page 698-704. ACM Press, (1994)Memory Reference Behavior of Compiler Optimized Programs on High Speed., and . ICPP (2), page 87-94. CRC Press, (1993)