Author of the publication

Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array.

, , , and . ASICON, page 1-4. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm., , , and . APCCAS, page 1753-1756. IEEE, (2006)Improving DFA on AES using all-fault ciphertexts., , , , , , and . ASICON, page 283-286. IEEE, (2017)The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUF., , , and . ITC-Asia, page 1-6. IEEE, (2021)Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology., , , , , and . IEICE Trans. Electron., 99-C (8): 974-983 (2016)Enhanced error correction against multiple-bit-upset based on BCH code for SRAM., , and . ASICON, page 1-4. IEEE, (2013)Flash-based Computing in-Memory Scheme for IOT., , , , , and . ASICON, page 1-4. IEEE, (2019)The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice., , , and . Microelectron. J., (February 2024)An in-Array Build-In Self-Test Scheme for Embedded SRAM Array., , and . IEEE Trans. Circuits Syst. II Express Briefs, 71 (8): 3935-3939 (August 2024)AHardware implementation of DES with combined countermeasure against DPA., , , , and . ASICON, page 1-4. IEEE, (2013)Post-bond test for TSVs using voltage division., , , and . ASICON, page 1-4. IEEE, (2015)