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An Efficient Accelerator of the Squaring for the Verifiable Delay Function Over a Class Group.

, , , , and . APCCAS, page 137-140. IEEE, (2020)

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Memory-reduced MAP decoding for double-binary convolutional Turbo code., , and . ISCAS, page 469-472. IEEE, (2010)Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes., and . ISCAS (6), page 5786-5789. IEEE, (2005)Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2156-2169 (2019)A lightweight face detector by integrating the convolutional neural network with the image pyramid., , , and . Pattern Recognit. Lett., (2020)Column-Weighted Probabilistic GDBF Decoder for Irregular LDPC Codes., , , and . ISVLSI, page 1-6. IEEE, (2023)An FPGA-Based Reconfigurable CNN Training Accelerator Using Decomposable Winograd., , , and . ISVLSI, page 1-6. IEEE, (2023)A Reconfigurable Accelerator for Generative Adversarial Network Training Based on FPGA., , , and . ISVLSI, page 144-149. IEEE, (2021)Accelerating NLP Tasks on FPGA with Compressed BERT and a Hardware-Oriented Early Exit Method., , , and . ISVLSI, page 410-413. IEEE, (2022)An Adaptive Chase-Pyndiah Algorithm for Turbo Product Codes., , , and . IEEE Commun. Lett., 27 (4): 1065-1069 (April 2023)A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator., , and . IEEE Trans. Circuits Syst., 67-I (10): 3484-3497 (2020)