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A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS.

R. Noguchi, K. Furuichi, H. Uemura, T. Inoue, A. Tsuchiya, K. Kishine, H. Katsurai, S. Nakano, and H. Nosaka. VLSI-DAT, page 1-4. IEEE, (2018)

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Keiji Kasai

Keiji Sayama

Other publications of authors with the same name

Frequency Discriminator Using a Simple AD Converter for Interface Systems.S. Kimura, A. Imajo, T. Inoue, A. Tsuchiya, and K. Kishine. ISOCC, page 128-129. IEEE, (2019)Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS.K. Kishine, H. Inaba, Y. Ohtomo, M. Nakamura, H. Koizumi, and M. Nakamura. MWSCAS, page 904-907. IEEE, (2013)Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers.S. Tanimura, A. Tsuchiya, T. Inoue, and K. Kishine. ASP-DAC, page 15-16. ACM, (2021)Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion.R. Yamazaki, T. Inoue, Y. Teramura, A. Tsuchiya, and K. Kishine. ICEIC, page 1-4. IEEE, (2022)Smart Computational Resource Distribution System with Automatic Classification Interface for CPS.Y. Teramura, T. Inoue, A. Tsuchiya, and K. Kishine. ISOCC, page 101-102. IEEE, (2022)A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks.T. Inoue, A. Tsuchiya, K. Kishine, D. Ito, Y. Takahashi, and M. Nakamura. ICECS, page 1-6. IEEE, (2021)Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS.K. Furuichi, H. Uemura, N. Koda, H. Inaba, and K. Kishine. ISOCC, page 261-262. IEEE, (2016)Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS.T. Inoue, A. Tsuchiya, K. Kishine, and M. Nakamura. ISOCC, page 77-78. IEEE, (2017)FPGA-based transceiver circuit for labeling signal transmission system.K. Nomura, N. Koda, T. Inoue, A. Tsuchiya, and K. Kishine. ISOCC, page 310-311. IEEE, (2017)Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier.S. Tanimura, A. Tsuchiya, R. Noguchi, T. Inoue, and K. Kishine. SoCC, page 161-164. IEEE, (2019)

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Disambiguation of "Kishine, Keiji"

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A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS.

Please choose a person to relate this publication to

Keiji Kasai

Keiji Sayama

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kishine, Keiji"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS.

Please choose a person to relate this publication to

Keiji Kasai

Keiji Sayama

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS.