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Reliability-Enhanced High-Level Synthesis using Memory Profiling and Fault Injection.

, , и . ISIE, стр. 1363-1370. IEEE, (2019)

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Peter Fibich

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Ernst Rudolf Christian Fibich

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Reliability-Enhanced High-Level Synthesis using Memory Profiling and Fault Injection., , и . ISIE, стр. 1363-1370. IEEE, (2019)Characterization of Interconnect Fault Effects in SRAM-based FPGAs., , и . DDECS, стр. 65-68. IEEE, (2023)Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu., , , , , и . SIES, стр. 1-4. IEEE, (2018)Vulnerability analysis of storage elements in HLS-generated designs using high-level profiling., , и . ICSRS, стр. 190-194. IEEE, (2017)HLshield: a reliability enhancement framework for high-level synthesis., , и . SIES, стр. 1-10. IEEE, (2017)Bitstream- Level Interconnect Fault Characterization for SRAM-based FPGAs., , и . DATE, стр. 1-2. IEEE, (2023)Device- and Temperature Dependency of Systematic Fault Injection Results in Artix-7 and iCE40 FPGAs., , и . DATE, стр. 1600-1605. IEEE, (2021)Evaluation of Open-Source Linear Algebra Libraries targeting ARM and RISC-V Architectures., , , и . FedCSIS, том 21 из Annals of Computer Science and Information Systems, стр. 663-672. (2020)Logic synthesis of assertions for saftey-critical applications., , , , и . ICIT, стр. 1581-1586. IEEE, (2015)Evaluation of Open-Source Linear Algebra Libraries in Embedded Applications., , , , , , , и . MECO, стр. 1-6. IEEE, (2019)