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Toward Efficient Low-Precision Training: Data Format Optimization and Hysteresis Quantization.

, , and . ICLR, OpenReview.net, (2022)

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Design techniques for ultra-efficient computing.. ISOCC, page 87-88. IEEE, (2016)A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS., , , , and . VLSI Circuits, page 1-2. IEEE, (2016)Enhancing Reliability of Analog Neural Network Processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (6): 1455-1459 (2019)Real-Time Denoising and Dereverberation wtih Tiny Recurrent U-Net., , , , , and . ICASSP, page 5789-5793. IEEE, (2021)Learning with Auxiliary Activation for Memory-Efficient Training., and . ICLR, OpenReview.net, (2023)Circuit techniques for miniaturized biomedical sensors., , , , , , , , , and 5 other author(s). CICC, page 1-7. IEEE, (2014)Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS., , , , and . APCCAS, page 734-735. IEEE, (2016)A low-power VGA full-frame feature extraction processor., , , , , and . ICASSP, page 2726-2730. IEEE, (2013)8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustment., , , , , and . ISSCC, page 148-149. IEEE, (2017)A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training., , and . ESSCIRC, page 145-148. IEEE, (2022)