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Disambiguation of "Leeser, Miriam"

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Exploiting GPU Direct Access to Non-Volatile Memory to Accelerate Big Data Processing.

, , and . HPEC, page 1-6. IEEE, (2020)

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Miriam Leeser

Manfred Leeser

Otto Leeser

Marcel Leeser

Rolf Leeser

 

Other publications of authors with the same name

High-Level and Compact Design of Cross-Channel LTE DownLink Channel Encoder., and . CrownCom, volume 261 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 15-24. Springer, (2018)Machine Learning Across Network-Connected FPGAs., , , , , and . HPEC, page 1-7. IEEE, (2023)Hardware Software Codesign of Applications on the Edge: Accelerating Digital PreDistortion for Wireless Communications., , , , and . HPEC, page 1-6. IEEE, (2022)Detection of Different Wireless Protocols on an FPGA with the Same Analog/RF Front End., , , , and . CrownCom, volume 261 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 25-35. Springer, (2018)Strategies and Demonstration to Support Multiple Wireless Protocols with a Single RF Front-End., , , , and . IEEE Wirel. Commun., 27 (3): 88-95 (2020)Machine Learning Aided Hardware Resource Estimation for FPGA DNN Implementations., , , and . IPDPS Workshops, page 77-83. IEEE, (2022)Computationally Efficient Look-up-Tables for Behavioral Modelling and Digital Pre-distortion of Multi-standard Wireless Systems., , , , , and . CrownCom/WiCON, volume 427 of Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, page 39-55. Springer, (2021)Optimizing Use of Different Types of Memory for FPGAs in High Performance Computing., , , and . HPEC, page 1-7. IEEE, (2020)3D CNN Acceleration on FPGA using Hardware-Aware Pruning., , , , , and . DAC, page 1-6. IEEE, (2020)Rothko: A Three-Dimensional FPGA., , , , , and . IEEE Des. Test Comput., 15 (1): 16-23 (1998)