( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array.

, , , и . IEEE Trans. Computers, 72 (12): 3416-3430 (декабря 2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Ai Cui

Yifang Cui

Keqiang Cui

Huiling Cui

Cui Jian

 

Другие публикации лиц с тем же именем

Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm., , , и . APCCAS, стр. 1753-1756. IEEE, (2006)Improving DFA on AES using all-fault ciphertexts., , , , , , и . ASICON, стр. 283-286. IEEE, (2017)Flash-based Computing in-Memory Scheme for IOT., , , , , и . ASICON, стр. 1-4. IEEE, (2019)Enhanced error correction against multiple-bit-upset based on BCH code for SRAM., , и . ASICON, стр. 1-4. IEEE, (2013)Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology., , , , , и . IEICE Trans. Electron., 99-C (8): 974-983 (2016)The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUF., , , и . ITC-Asia, стр. 1-6. IEEE, (2021)An in-Array Build-In Self-Test Scheme for Embedded SRAM Array., , и . IEEE Trans. Circuits Syst. II Express Briefs, 71 (8): 3935-3939 (августа 2024)The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice., , , и . Microelectron. J., (февраля 2024)Post-bond test for TSVs using voltage division., , , и . ASICON, стр. 1-4. IEEE, (2015)AHardware implementation of DES with combined countermeasure against DPA., , , , и . ASICON, стр. 1-4. IEEE, (2013)