( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.

, , , , , , , , , , , и . ISSCC, стр. 500-501. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Weiwei Tian

Weiwei Chen

Shan-Shan Zhan

Weiwei Cheng

Weiwei Wang

 

Другие публикации лиц с тем же именем

Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion., , и . ACM Great Lakes Symposium on VLSI, стр. 105-110. ACM, (2018)An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS., , , , и . A-SSCC, стр. 1-3. IEEE, (2021)VLSI design of a reconfigurable S-box based on memory sharing method., , , и . IEICE Electron. Express, 11 (1): 20130872 (2014)IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits., , и . ISCAS, стр. 1-5. IEEE, (2023)HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS., , , и . A-SSCC, стр. 209-212. IEEE, (2017)A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications., , , , и . A-SSCC, стр. 205-208. IEEE, (2017)A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator., , , , , , и . A-SSCC, стр. 1-4. IEEE, (2018)A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms., , , , , , , и . DAC, стр. 176:1-176:6. ACM, (2014)A Depthwise Separable Convolution Neural Network for Small-footprint Keyword Spotting Using Approximate MAC Unit and Streaming Convolution Reuse., , и . APCCAS, стр. 309-312. IEEE, (2019)Multi-Task Evolutionary to PVT Knowledge Transfer for Analog Integrated Circuit Optimization., , , , , и . ICCAD, стр. 1-9. IEEE, (2023)