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Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits., , , and . ISCAS, page 1484-1487. IEEE, (2010)Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI., , and . LASCAS, page 1-4. IEEE, (2018)Analysis and Design of RF Energy-Harvesting Systems With Impedance-Aware Rectifier Sizing., , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (2): 361-365 (February 2023)Methodology for Performance Optimization in Noise- and Distortion-Canceling LNA., , , , , and . SMACD, page 45-48. IEEE, (2019)Impact of Technology Scaling on Digital Subthreshold Circuits., , , and . ISVLSI, page 179-184. IEEE Computer Society, (2008)Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs., , , , and . SBCCI, page 26-. IEEE Computer Society, (2003)Operational Amplifier Power Optimization for a Given Total (Slewing plus Linear) Settling Time., and . SBCCI, page 247-253. IEEE Computer Society, (2002)DNA electrical detection based on inductor resonance frequency in standard CMOS technology., , , , , , and . ESSCIRC, page 337-340. IEEE, (2003)Glitch-induced within-die variations of dynamic energy in voltage-scaled nano-CMOS circuits., , , , and . ESSCIRC, page 518-521. IEEE, (2010)A 1.1- / 0.9-nA Temperature-Independent 213- / 565-ppm/$^\circ$C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI., , and . CoRR, (2023)