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Optimization of AI SoC with Compiler-assisted Virtual Design Platform.

, , , , and . ISPD, page 187-193. ACM, (2023)

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High-speed C-testable systolic array design for Galois-field inversion., and . ED&TC, page 342-346. IEEE Computer Society, (1997)A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters., , , , , , , and . Asian Test Symposium, page 103-. IEEE Computer Society, (2001)Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip., , , , , and . Asian Test Symposium, page 91-96. IEEE Computer Society, (2001)Optimization of regular expression pattern matching circuits on FPGA., , , and . DATE Designers' Forum, page 12-17. European Design and Automation Association, Leuven, Belgium, (2006)Hardware/software co-designed accelerator for vector graphics applications., , , , , and . SASP, page 108-114. IEEE Computer Society, (2011)A prototype of a wireless-based test system., , , , , , , , , and 2 other author(s). SoCC, page 225-228. IEEE, (2007)RAMSES: A Fast Memory Fault Simulator., , and . DFT, page 165-173. IEEE Computer Society, (1999)Application-level embedded communication tracer for many-core systems., , , and . ASP-DAC, page 803-808. IEEE, (2015)Optimization of Pattern Matching Circuits for Regular Expression on FPGA., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (12): 1303-1310 (2007)Fast DNN-based Mechatronics Prototyping Platform on Robotic Arm Control., , , , and . AICAS, page 506. IEEE, (2022)