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Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead.

, , and . ETS, page 53-58. IEEE Computer Society, (2009)

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Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead., , and . ETS, page 53-58. IEEE Computer Society, (2009)Enabling pervasive encryption through IBM Z stack innovations., , , , , , , , , and 6 other author(s). IBM J. Res. Dev., 62 (2/3): 2:1-2:11 (2018)Scan Test Planning for Power Reduction., , , , and . DAC, page 521-526. IEEE, (2007)Low-power test planning for arbitrary at-speed delay-test clock schemes., and . VTS, page 93-98. IEEE Computer Society, (2010)Integrating Scan Design and Soft Error Correction in Low-Power Applications., , and . IOLTS, page 59-64. IEEE Computer Society, (2008)Efficient fault simulation on many-core processors., , , and . DAC, page 380-385. ACM, (2010)Energy Efficiency Boost in the AI-Infused POWER10 Processor., , , , , , , , , and 16 other author(s). ISCA, page 29-42. IEEE, (2021)Programmable deterministic Built-In Self-Test., , , , , , and . ITC, page 1-9. IEEE Computer Society, (2007)BIST Power Reduction Using Scan-Chain Disable in the Cell Processor., , , and . ITC, page 1-8. IEEE Computer Society, (2006)Scan chain clustering for test power reduction., , , , , and . DAC, page 828-833. ACM, (2008)