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Disambiguation of "Fernando, Pradeep"

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Customizable FPGA IP Core Implementation of a General-Purpose Genetic Algorithm Engine.

, , , , and . IEEE Trans. Evol. Comput., 14 (1): 133-149 (2010)

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Pradeep Pareek

Pradeep Itty

Pradeep Punnakal

Pradeep Chakkarath

Pradeep Ajit Dhillon

 

Other publications of authors with the same name

RoboGen: Robot Generation through Artificial Evolution., , , , , , , , , and . ALIFE, page 136-137. MIT Press, (2014)Customizable FPGA IP Core Implementation of a General-Purpose Genetic Algorithm Engine., , , , and . IEEE Trans. Evol. Comput., 14 (1): 133-149 (2010)Scheduling HPC Workflows with Intel Optane Persistent Memory., , , , and . IPDPS Workshops, page 56-65. IEEE, (2021)A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine., , , , , , and . IPDPS, page 1-8. IEEE, (2008)Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core., , , , , , , and . ICES, volume 5216 of Lecture Notes in Computer Science, page 225-236. Springer, (2008)Sparkle: optimizing spark for large memory machines and analytics., , , , , , , , , and . SoCC, page 656. ACM, (2017)Persistence and Synchronization: Friends or Foes?, , , , and . CoRR, (2020)Adding Persistence to Main Memory Programming.. Georgia Institute of Technology, Atlanta, GA, USA, (2021)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/64530).An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning., and . VLSI Design, page 337-342. IEEE Computer Society, (2008)Self-Reconfigurable Analog Array Integrated Circuit Architecture for Space Applications., , , , , , , and . AHS, page 83-90. IEEE Computer Society, (2008)