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HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches.

C. Escuin, A. Khan, P. Ibáñez, T. Monreal, V. Viñals, и J. Castrillón. DroneSE/RAPIDO@HiPEAC, стр. 53-58. ACM, (2022)

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Alfredo Ibáñez

Marcela Ibáñez

Fernando Ibáñez Walker

Aurélien Ibanez

Roberto Ibañez

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Exploiting reuse locality on inclusive shared last-level caches.J. Albericio, P. Ibáñez, V. Viñals, и J. Llabería. ACM Trans. Archit. Code Optim., 9 (4): 38:1-38:19 (2013)Near-optimal replacement policies for shared caches in multicore processors.J. Díaz, P. Ibáñez, T. Monreal, V. Viñals, и J. Llabería. J. Supercomput., 77 (10): 11756-11785 (2021)Exposing Abstraction-Level Interactions with a Parallel Ray Tracer.A. Valero, D. Gracia, R. Tejero, L. Ramos, A. Navarro-Torres, A. Muñoz, J. Ezpeleta, J. Briz, A. Murillo, E. Montijano и 7 other автор(ы). WCAE@ISCA, стр. 5:1-5:8. ACM, (2019)BALANCER: bandwidth allocation and cache partitioning for multicore processors.A. Navarro-Torres, J. Alastruey-Benedé, P. Ibáñez, и V. Yúfera. J. Supercomput., 79 (9): 10252-10276 (июня 2023)Characterization and Improvement of Load/Store Cache-based Prefetching.P. Ibáñez, V. Viñals, J. Briz, и M. Garzarán. International Conference on Supercomputing, стр. 369-376. ACM, (1998)Counteracting Bank Misprediction in Sliced First-Level Caches.E. Torres, P. Ibáñez, V. Viñals, и J. Llabería. Euro-Par, том 2790 из Lecture Notes in Computer Science, стр. 586-596. Springer, (2003)Speeding-Up Synchronizations in DSM Multiprocessors.A. Hernández, B. Fernández, P. Ibáñez, V. Viñals, и J. Llabería. Euro-Par, том 4128 из Lecture Notes in Computer Science, стр. 473-484. Springer, (2006)Forecasting lifetime and performance of a novel NVM last-level cache with compression.C. Escuin, P. Ibáñez, T. Monreal, J. Llabería, и V. Viñals. CoRR, (2022)Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding.J. Herruzo, S. González-Navarro, P. Ibáñez, V. Viñals, J. Alastruey-Benedé, и O. Plata. DCC, стр. 577. IEEE, (2019)Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers.B. Sahelices, A. Hernández, P. Ibáñez, V. Yúfera, и J. Llabería. J. Comput. Sci. Technol., 27 (1): 75-91 (2012)

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