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Simulation for the Feasibility of IGZO Channel in 3D Vertical FeFET Memory Based on TCAD.

Z. Du, C. Sun, X. Dou, P. Sang, X. Zhan, C. Jin, J. Wu, and J. Chen. ICTA, page 51-52. IEEE, (2023)

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Chen Chen

Shih Chen Chen

Yi-Chen Chen

Chen-Loung Chen

Other publications of authors with the same name

Bits Mapping in Triple-level-cell (TLC) Charge-trap (CT) 3D NAND Flash Memory and its Applications to IoT Security.Y. Xi, X. Fang, Y. Kong, Y. Guo, H. Lin, X. Zhan, and J. Chen. ICTA, page 69-71. IEEE, (2021)Grain Size Reduction of Ferroelectric HZO Enabled by a Novel Solid Phase Epitaxy (SPE) Approach: Working Principle, Experimental Demonstration, and Theoretical Understanding.D. Zhang, J. Wu, Q. Kong, Z. Zhou, L. Liu, K. Han, C. Sun, X. Wang, G. Liu, L. Jiao and 4 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Program/Erase Cycling Enhanced Lateral Charge Diffusion in Triple-Level Cell Charge-Trapping 3D NAND Flash Memory.R. Cao, J. Wu, W. Yang, J. Chen, and X. Jiang. IRPS, page 1-4. IEEE, (2019)One-shot Read Processing to Enhance Cold Data Retention in Charge-trap TLC 3D NAND Flash.S. Yang, X. Zhao, K. Xie, X. Zhan, J. Wu, and J. Chen. ASICON, page 1-4. IEEE, (2023)An Artificial Intelligence Approach to Price Design for Improving AQM Performance.H. Wang, J. Chen, C. Liao, and Z. Tian. GLOBECOM, page 1-5. IEEE, (2011)Scaling Behaviour of State-to-State Coupling During Hole Trapping at Si/SiO2.X. Ma, X. Jiang, J. Chen, L. Wang, and Y. En. IRPS, page 1-4. IEEE, (2019)Simulation for the Feasibility of IGZO Channel in 3D Vertical FeFET Memory Based on TCAD.Z. Du, C. Sun, X. Dou, P. Sang, X. Zhan, C. Jin, J. Wu, and J. Chen. ICTA, page 51-52. IEEE, (2023)Opto-Electronic Monolayer ZnO Memristor Produced via Low Temperature Atomic Layer Deposition.J. Mei, B. Chen, P. Sang, J. Wu, X. Zhan, and J. Chen. ICTA, page 53-54. IEEE, (2023)First Demonstration of BEOL-Compatible 3D Vertical FeNOR.Y. Feng, D. Zhang, C. Sun, Z. Zheng, Y. Chen, Q. Kong, G. Liu, Y. Kang, K. Han, Z. Zhou and 5 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2024)Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory.F. Wang, Y. Li, X. Ma, and J. Chen. IEEE Access, (2021)

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Disambiguation of "Chen, Jiezhi"

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Simulation for the Feasibility of IGZO Channel in 3D Vertical FeFET Memory Based on TCAD.

Please choose a person to relate this publication to

Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Chen-Loung Chen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chen, Jiezhi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Simulation for the Feasibility of IGZO Channel in 3D Vertical FeFET Memory Based on TCAD.

Please choose a person to relate this publication to

Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

Chen-Loung Chen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Simulation for the Feasibility of IGZO Channel in 3D Vertical FeFET Memory Based on TCAD.