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Fast and accurate resource estimation of RTL-based designs targeting FPGAS., and . FPL, page 59-64. IEEE, (2008)Fast RTL Power Estimation for FPGA Designs., , , , and . FPL, page 343-348. IEEE Computer Society, (2011)Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs., , , , and . FPL, page 391-396. IEEE, (2005)A scalable, multi-stream MPEG-4 video decoder for conferencing and surveillance applications., , , , , , and . ICIP (2), page 886-889. IEEE, (2005)An efficient optimized JPEG 2000 tier-1 coder hardware implementation.. VCIP, volume 5150 of Proceedings of SPIE, page 1089-1096. SPIE, (2003)On mutual information for observation-to-observation association., , , and . FUSION, page 1293-1298. IEEE, (2015)A Single Program Multiple Data Parallel Processing Platform for FPGAs., , and . FCCM, page 302-303. IEEE Computer Society, (2004)A Virtual Socket Framework for Rapid Emulation of Video and Multimedia Designs., , , and . ICME, page 872-875. IEEE Computer Society, (2005)High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder., , , and . PATMOS, volume 2799 of Lecture Notes in Computer Science, page 440-450. Springer, (2003)Communication Primitives Driven Hardware Design and Test Methodology Applied on Complex Video Applications., , , , and . IEEE International Workshop on Rapid System Prototyping, page 246-249. IEEE Computer Society, (2005)