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Decentralized Device Authentication Model using the Trust Score and Blockchain Technology for Dynamic Networks.

, , , and . Blockchain, page 116-125. IEEE, (2020)

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HORNSAT, Model Checking, Verification and games (Extended Abstract)., , and . CAV, volume 1102 of Lecture Notes in Computer Science, page 99-110. Springer, (1996)Abstraction of polychronous dataflow specifications into mode-automata., , and . ICSAMOS, page 33-40. IEEE, (2013)SMT based false causal loop detection during code synthesis from Polychronous specifications., , , and . MEMOCODE, page 109-118. IEEE, (2011)Formal Hardware Verification of InfoSec Primitives., and . ISVLSI, page 140-145. IEEE, (2019)MCBCG: Model Checking Based Sequential Clock-Gating., and . HLDVT, page 20-25. IEEE Computer Society, (2009)On the Complexity of Relational Problems for Finite State Processes (Extended Abstract)., , , and . ICALP, volume 1099 of Lecture Notes in Computer Science, page 466-477. Springer, (1996)Formal Transformation of a KPN Specification to a GALS Implementation., , , and . FDL, page 84-89. IEEE, (2008)Flexible Composite Galois Field GF((2^m)^2) Multiplier Designs., and . VDAT, volume 711 of Communications in Computer and Information Science, page 3-14. Springer, (2017)A Formally Verified Peak-Power Reduction Technique for Hardware Synthesis from Concurrent Action-Oriented Specifications., , and . J. Low Power Electron., 5 (2): 135-144 (2009)Using probabilistic model checking for dynamic power management., , , , and . Formal Aspects Comput., 17 (2): 160-176 (2005)