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Orthrus: efficient software integrity protection on multi-cores.

, , and . ASPLOS, page 371-384. ACM, (2010)

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Using Information Flow to Design an ISA that Controls Timing Channels., , and . CSF, page 272-287. IEEE, (2019)Systematic Security Assessment at an Early Processor Design Stage., , , and . TRUST, volume 6740 of Lecture Notes in Computer Science, page 154-171. Springer, (2011)On the performance of averaged optimal routing., , and . CISS, page 1-6. IEEE, (2012)SecDCP: secure dynamic cache partitioning for efficient timing channel protection., , , , and . DAC, page 74:1-74:6. ACM, (2016)High-performance parallel accelerator for flexible and efficient run-time monitoring., and . DSN, page 1-12. IEEE Computer Society, (2012)Flash Memory for Ubiquitous Hardware Security Functions: True Random Number Generation and Device Fingerprints., , , , , and . IEEE Symposium on Security and Privacy, page 33-47. IEEE Computer Society, (2012)AEGIS: a single-chip secure processor.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2005)ndltd.org (oai:dspace.mit.edu:1721.1/34469).Execution time prediction for energy-efficient hardware accelerators., , and . MICRO, page 457-469. ACM, (2015)MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration., , , and . CoRR, (2020)SoftVN: efficient memory protection via software-provided version numbers., , , and . ISCA, page 160-172. ACM, (2022)