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NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.

N. Kocaman, U. Singh, B. Raghavan, A. Iyer, K. Thasari, S. Surana, J. Jung, J. Jeong, H. Zhang, A. Vasani, Y. Shim, Z. Huang, A. Garg, H. bin Lee, B. Wu, F. Liu, R. Wang, M. Loh, A. Wang, M. Caresosa, B. Zhang, and A. Momtaz. ISSCC, page 120-122. IEEE, (2022)

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Neil Garg

Animesh Garg

Martin Garg

Dineshkumar Garg

Priya Garg

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A high speed complex adaptive filter for an asymmetric wireless LAN using a new quantized polynomial representation.A. Garg, I. Steiner, G. Jullien, J. Haslett, and G. McGibney. ISCAS (2), page 157-160. IEEE, (2003)2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS.U. Singh, A. Garg, B. Raghavan, N. Huang, H. Zhang, Z. Huang, A. Momtaz, and J. Cao. ISSCC, page 40-41. IEEE, (2014)18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS.G. Li, A. Garg, T. He, U. Singh, J. Zhang, L. Rao, C. Liu, M. Nazari, Y. Liu, Y. Liu and 9 other author(s). ISSCC, page 338-340. IEEE, (2024)A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS.B. Zhang, A. Nazemi, A. Garg, N. Kocaman, M. Ahmadi, M. Khanpour, H. Zhang, J. Cao, and A. Momtaz. ISSCC, page 34-35. IEEE, (2013)A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS.A. Garg, U. Singh, N. Huang, W. Wong, B. Liu, Z. Huang, A. Momtaz, and J. Cao. VLSIC, page 1-2. IEEE, (2014)20.2 A 16TX/16RX 60GHz 802.11ad chipset with single coaxial interface and polarization diversity.M. Boers, I. Vassiliou, S. Sarkar, S. Nicolson, E. Adabi, B. Afshar, B. Perumana, T. Chalvatzis, S. Kavadias, P. Sen and 32 other author(s). ISSCC, page 344-345. IEEE, (2014)An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.N. Kocaman, U. Singh, B. Raghavan, A. Iyer, K. Thasari, S. Surana, J. Jung, J. Jeong, H. Zhang, A. Vasani and 12 other author(s). ISSCC, page 120-122. IEEE, (2022)

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Disambiguation of "Garg, Adesh"

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An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.

Please choose a person to relate this publication to

Neil Garg

Animesh Garg

Martin Garg

Dineshkumar Garg

Priya Garg

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Garg, Adesh"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.

Please choose a person to relate this publication to

Neil Garg

Animesh Garg

Martin Garg

Dineshkumar Garg

Priya Garg

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology.