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Phase-based Cache Locking for Embedded Systems.

, and . ACM Great Lakes Symposium on VLSI, page 115-120. ACM, (2015)

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Analysis of cache tuner architectural layouts for multicore embedded systems., , and . IPCCC, page 1-8. IEEE Computer Society, (2014)Configuration prefetching and reuse for preemptive hardware multitasking on partially reconfigurable FPGAs., , and . DATE, page 1505-1508. IEEE, (2016)Energy Prediction for Cache Tuning in Embedded Systems., , and . ICCD, page 630-637. IEEE, (2019)Formulation-level design space exploration for partially reconfigurable FPGAs., and . FPT, page 1-6. IEEE, (2011)TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems., and . Computers, 7 (1): 3 (2018)A table-based method for single-pass cache optimization., , , and . ACM Great Lakes Symposium on VLSI, page 71-76. ACM, (2008)Design Framework for Partial Run-Time FPGA Reconfiguration., , and . ERSA, page 122-128. CSREA Press, (2008)Overlay-based side-channel countermeasures: A case study on correlated noise generation., , and . MWSCAS, page 1308-1311. IEEE, (2017)Low-Energy Instruction Cache Optimization Techniques for Embedded Systems., and . Handbook of Energy-Aware and Green Computing, Chapman and Hall/CRC, (2012)A single-pass cache simulation methodology for two-level unified caches., and . ISPASS, page 168-177. IEEE Computer Society, (2012)