( en | de | ru )

 

Disambiguation of "Dabos, George"

Author of the publication

copydeleteadd this publication to your clipboard
O-band Silicon Photonics 8×8 Arrayed Waveguide Grating Router (AWGR) for 1.6 Tb/s On-chip Routing.

, , , , , , , , and . OFC, page 1-3. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

George Mertzios

Combinatorial optimization and recognition of graph classes with applications to related models. TU Aachen, (2009)

George Perret

George Anderson

Witold George

Hans George

 

Other publications of authors with the same name

Integrated photonic and plasmonic circuits for optical interconnect applications. Aristotle University Of Thessaloniki, Greece, (2018)National Archive of PhD Theses: oai:10442/44291.Time-series classification with an all-optical recurrent neuron., , , , , and . ECOC, page 1-4. IEEE, (2020)DDOS attack identification via a silicon photonic Deep Neural Network with 50 GHz input and weight update., , , , , , , , , and 4 other author(s). OFC, page 1-3. IEEE, (2023)Compute with Light: Architectures, Technologies and Training Models for Neuromorphic Photonic Circuits., , , , , , , , , and . ECOC, page 1-4. IEEE, (2021)O-band Silicon Photonics 8×8 Arrayed Waveguide Grating Router (AWGR) for 1.6 Tb/s On-chip Routing., , , , , , , , and . OFC, page 1-3. IEEE, (2018)Scaling Optical Interconnects Beyond 400 Gb/s., , , , , , , , , and 11 other author(s). ECOC, page 1-3. IEEE, (2018)Eight-channel second-order ring resonator based SOI multiplexers/demultiplexers for optical interconnects., , , , , , , , , and . ECOC, page 1-3. IEEE, (2014)Plasmonic Waveguides Co-Integrated with Si3N4 Waveguide Platform for Integrated Biosensors., , , , , , , , , and 4 other author(s). ICTON, page 1. IEEE, (2019)Low-cost vertical coupling schemes for optical I/Os and 3D integration in CMOS photonic integrated circuits., , , and . ICTON, page 1-4. IEEE, (2017)Photonic Neuromorphic Computing: Architectures, Technologies, and Training Models., , , , , , , , , and . OFC, page 1-3. IEEE, (2022)