( en | de | ru )

 

Disambiguation of "Rajamanickam, Sivasankaran"

Author of the publication

copydeleteadd this publication to your clipboard
Scalable Triangle Counting on Distributed-Memory Systems.

, , , , and . HPEC, page 1-5. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jeyaganesh Rajamanickam

 

Other publications of authors with the same name

Performance Portable Supernode-based Sparse Triangular Solver for Manycore Architectures., , and . ICPP, page 70:1-70:11. ACM, (2020)A Portable SIMD Primitive Using Kokkos for Heterogeneous Architectures., , , and . WACCPD@SC, volume 12017 of Lecture Notes in Computer Science, page 140-163. Springer, (2019)A Study of Mixed Precision Strategies for GMRES on GPUs., , , , and . CoRR, (2021)Multi-threaded Sparse Matrix-Matrix Multiplication for Many-Core and GPU Architectures., , and . CoRR, (2018)TenSQL: An SQL Database Built on GraphBLAS., , , and . HPEC, page 1-8. IEEE, (2023)An Experimental Study of Two-level Schwarz Domain-Decomposition Preconditioners on GPUs., , and . IPDPS, page 680-689. IEEE, (2023)Basker: A Threaded Sparse LU Factorization Utilizing Hierarchical Parallelism and Data Layouts., , and . IPDPS Workshops, page 673-682. IEEE Computer Society, (2016)ShyLU: A Hybrid-Hybrid Solver for Multicore Platforms., , and . IPDPS, page 631-643. IEEE Computer Society, (2012)Scalable Inference for Sparse Deep Neural Networks using Kokkos Kernels., and . HPEC, page 1-7. IEEE, (2019)A Hybrid Approach for Parallel Transistor-Level Full-Chip Circuit Simulation., and . VECPAR, volume 8969 of Lecture Notes in Computer Science, page 102-111. Springer, (2014)