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A Novel Polymorphic Gate Based Circuit Fingerprinting Technique.

, , , , , , and . ACM Great Lakes Symposium on VLSI, page 141-146. ACM, (2018)

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Don't Forget to Sign the Gradients!, , and . MLSys, mlsys.org, (2021)Building Hardware Security Primitives Using Scan-based Design-for-Testability., , and . MWSCAS, page 1-6. IEEE, (2022)A Novel Polymorphic Gate Based Circuit Fingerprinting Technique., , , , , , and . ACM Great Lakes Symposium on VLSI, page 141-146. ACM, (2018)Balancing Testability and Security by Configurable Partial Scan Design., , , and . ITC-Asia, page 145-150. IEEE, (2018)Impacts of Machine Learning on Counterfeit IC Detection and Avoidance Techniques., and . ISQED, page 352-357. IEEE, (2020)Invited: Independent Verification and Validation of Security-Aware EDA Tools and IP., , , , , , , , , and 3 other author(s). DAC, page 1299-1302. IEEE, (2021)A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates., , , , , and . AsianHOST, page 1-4. IEEE, (2021)Efficient Transfer Learning on Modeling Physical Unclonable Functions., , , and . ISQED, page 1-6. IEEE, (2020)Provably Accurate Memory Fault Detection Method for Deep Neural Networks., and . ACM Great Lakes Symposium on VLSI, page 443-448. ACM, (2021)AID: Attesting the Integrity of Deep Neural Networks., , and . DAC, page 19-24. IEEE, (2021)