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Disambiguation of "Nakamura, Ken"

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Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure.

, , , , , , , , , , , , and . Hot Chips Symposium, page 1-24. IEEE, (2015)

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Shin'ichiro Nakamura

Makoto Nakamura

Akira Nakamura

Ken Lau

Ken Endo

 

Other publications of authors with the same name

An HEVC real-time encoding system with high quality HDR color representations., , , , , , and . ICCE, page 1-2. IEEE, (2018)A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems., , , , , , , , , and . CICC, page 177-180. IEEE, (2003)A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K., , , , , , , , , and 3 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 26 (10): 1930-1938 (2018)Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability., , , , , , , , , and 5 other author(s). VLSIC, page 54-. IEEE, (2015)A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation., , , , and . ISCAS, page 1-5. IEEE, (2019)Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture., , , , , , , and . COOL CHIPS, page 1-3. IEEE, (2019)OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization., , , , , , , and . MWSCAS, page 1-4. IEEE, (2022)An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture., , , , , , , and . COOL CHIPS, page 1-3. IEEE, (2022)Super high resolution video codec system with multiple MPEG-s HDTV codec LSI's., , and . ISCAS (3), page 793-796. IEEE, (2004)A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders., , , , , , , and . PDCAT, volume 13798 of Lecture Notes in Computer Science, page 288-300. Springer, (2022)