( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET.

, , , , , , , , , , , , , и . ISSCC, стр. 120-122. IEEE, (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Huynh Van Van

Eligius Vancek

Viktor Vanberg

Roland Vandieken

Helga Vandersee

 

Другие публикации лиц с тем же именем

An adaptive 4-PAM decision-feedback equalizer for chip-to-chip signaling., , и . SoCC, стр. 297-300. IEEE, (2004)A 5Gb/s Transmitter with Reflection Cancellation for Backplane Transceivers., , , , и . CICC, стр. 413-416. IEEE, (2006)A 3.2Gb/s Semi-Blind-Oversampling CDR., , , и . ISSCC, стр. 1304-1313. IEEE, (2006)Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (5): 1306-1315 (2008)The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System., , , , и . FPGA, стр. 53-61. ACM, (1997)A 4-Lane 1.25-to-28.05Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 106-108. IEEE, (2018)11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 181-183. IEEE, (2021)A Field Programmable Accelerator for Compiled-Code Applications., , и . ICCD, стр. 491-496. IEEE Computer Society, (1993)An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 352-354. IEEE, (2011)Signaling capacity of FR4 PCB traces for chip-to-chip communication., , , и . ISCAS (5), стр. 85-88. IEEE, (2003)