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Customizing IP cores for system-on-chip designs using extensive external don't-cares.

, , and . DATE, page 582-585. IEEE, (2009)

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Accurately Handle Don't-Care Conditions in High-Level Designs and Application for Reducing Initialized Registers., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (4): 646-651 (2010)InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization., , , and . ISQED, page 487-494. IEEE Computer Society, (2007)Fixing Design Errors with Counterexamples and Resynthesis., , and . ASP-DAC, page 944-949. IEEE Computer Society, (2007)Reap what you sow: spare cells for post-silicon metal fix., , and . ISPD, page 103-110. ACM, (2008)Improving gate-level simulation accuracy when unknowns exist., and . DAC, page 936-940. ACM, (2012)Enhancing bug hunting using high-level symbolic simulation., , , , and . ACM Great Lakes Symposium on VLSI, page 417-420. ACM, (2009)Automatic Partitioner for Behavior Level Distributed Logic Simulation., , , , , and . FORTE, volume 3731 of Lecture Notes in Computer Science, page 525-528. Springer, (2005)Optimizing blocks in an SoC using symbolic code-statement reachability analysis., , and . ASP-DAC, page 787-792. IEEE, (2010)Customizing IP cores for system-on-chip designs using extensive external don't-cares., , and . DATE, page 582-585. IEEE, (2009)Reducing test point overhead with don't-cares., , , and . MWSCAS, page 534-537. IEEE, (2012)