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A Complexity-Effective Out-of-Order Retirement Microarchitecture, , , , и . IEEE Transactions on Computers, (5555)A Neural Network to Estimate Isolated Performance from Multi-Program Execution., , , , и . PDP, стр. 63-66. IEEE, (2022)Cache-Poll: Containing Pollution in Non-Inclusive Caches Through Cache Partitioning., , , и . ICPP, стр. 33:1-33:11. ACM, (2022)A Dynamic Power-Aware Partitioner with Task Migration for Multicore Embedded Systems., , , , и . Euro-Par (1), том 6852 из Lecture Notes in Computer Science, стр. 218-229. Springer, (2011)Student Research Poster: A Low Complexity Cache Sharing Mechanism to Address System Fairness., , , и . PACT, стр. 455. ACM, (2016)A power-aware hybrid RAM-CAM renaming mechanism for fast recovery., , , и . ICCD, стр. 150-157. IEEE Computer Society, (2009)OMHI 2012: First International Workshop on On-chip Memory Hierarchies and Interconnects: Organization, Management and Implementation., , и . Euro-Par Workshops, том 7640 из Lecture Notes in Computer Science, стр. 305-306. Springer, (2012)The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures., , , , и . IPDPS, стр. 1-11. IEEE, (2008)Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance., , , и . IEEE Trans. Computers, 68 (10): 1442-1454 (2019)A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions., , , , и . IEEE Trans. Parallel Distributed Syst., 23 (8): 1361-1368 (2012)