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Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement.

, , , , , and . ICS, page 433-442. ACM, (2013)

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Using Indexing Functions to Reduce Conflict Aliasing in Branch Prediction Tables., , and . IEEE Trans. Computers, 55 (8): 1057-1061 (2006)Persist Level Parallelism: Streamlining Integrity Tree Updates for Secure Persistent Memory., , , and . MICRO, page 14-27. IEEE, (2020)Optimizing Dual-Core Execution for Power Efficiency and Transient-Fault Recovery., , , and . IEEE Trans. Parallel Distributed Syst., 18 (8): 1080-1093 (2007)Exploiting Quantum Assertions for Error Mitigation and Quantum Program Debugging., , , and . ICCD, page 124-131. IEEE, (2022)In-Place Zero-Space Memory Protection for CNN., , , , , and . NeurIPS, page 5735-5744. (2019)Tuning Stencil codes in OpenCL for FPGAs., and . ICCD, page 249-256. IEEE Computer Society, (2016)Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation., , and . ASPLOS, page 1017-1030. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..Salus: Efficient Security Support for CXL-Expanded GPU Memory., , , and . HPCA, page 1-15. IEEE, (2024)Locality-Driven Dynamic GPU Cache Bypassing., , , , , and . ICS, page 67-77. ACM, (2015)Exploiting uniform vector instructions for GPGPU performance, energy efficiency, and opportunistic reliability enhancement., , , , , and . ICS, page 433-442. ACM, (2013)