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RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference.

L. Wang, J. An, W. Ye, W. Li, H. Gao, Y. He, J. Gao, J. Yue, L. Fan, and C. Dou. APCCAS, page 497-500. IEEE, (2022)

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Jinshan Liu

Jinshan Zhang

Haidi Yue

Chaofang Yue

Jenny Yuen

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STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration.J. Yue, Y. Liu, R. Liu, W. Sun, Z. Yuan, Y. Tu, Y. Chen, A. Ren, Y. Wang, M. Chang and 2 other author(s). IEEE J. Solid State Circuits, 56 (6): 1936-1948 (2021)STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS.Z. Yuan, Y. Liu, J. Yue, Y. Yang, J. Wang, X. Feng, J. Zhao, X. Li, and H. Yang. IEEE J. Solid State Circuits, 55 (2): 465-477 (2020)A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity.H. Wu, Y. Chen, Y. Yuan, J. Yue, X. Fu, Q. Ren, Q. Luo, P. Mak, X. Wang, and F. Zhang. IEEE Trans. Circuits Syst. I Regul. Pap., 71 (2): 689-702 (February 2024)Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge.J. An, Z. Zhou, L. Wang, W. Ye, W. Li, H. Gao, Z. Li, J. Tian, Y. Wang, H. Hu and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 32 (2): 283-290 (February 2024)A Weight-Reload-Eliminated Compute-in-Memory Accelerator for 60 fps 4K Super-Resolution.Y. Li, J. Yue, J. Wang, C. Tang, Y. He, W. Jia, K. Zou, L. Zhang, H. Yang, and Y. Liu. IEEE Trans. Circuits Syst. II Express Briefs, 70 (3): 1179-1183 (March 2023)A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture.J. Yue, C. He, Z. Wang, Z. Cong, Y. He, M. Zhou, W. Sun, X. Li, C. Dou, F. Zhang and 3 other author(s). ISSCC, page 252-253. IEEE, (2023)A 28nm 2D/3D Unified Sparse Convolution Accelerator with Block-Wise Neighbor Searcher for Large-Scaled Voxel-Based Point Cloud Network.W. Sun, X. Feng, C. Tang, S. Fan, Y. Yang, J. Yue, H. Yang, and Y. Liu. ISSCC, page 328-329. IEEE, (2023)A Sort-Less FPGA-Based Non-Maximum Suppression Accelerator using Multi-Thread Computing and Binary Max Engine for Object Detection.C. Fang, H. Derbyshire, W. Sun, J. Yue, H. Shi, and Y. Liu. A-SSCC, page 1-3. IEEE, (2021)A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM.G. Yin, Y. Chen, M. Lee, X. Du, Y. Ke, W. Tang, Z. Chen, M. Zhou, J. Yue, H. Yang and 3 other author(s). CICC, page 1-2. IEEE, (2024)PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors.J. Li, Y. Liu, H. Li, Z. Yuan, C. Fu, J. Yue, X. Feng, C. Xue, J. Hu, and H. Yang. IEEE Trans. Very Large Scale Integr. Syst., 26 (9): 1671-1684 (2018)

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Disambiguation of "Yue, Jinshan"

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RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference.

Please choose a person to relate this publication to

Jinshan Liu

Jinshan Zhang

Haidi Yue

Chaofang Yue

Jenny Yuen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yue, Jinshan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference.

Please choose a person to relate this publication to

Jinshan Liu

Jinshan Zhang

Haidi Yue

Chaofang Yue

Jenny Yuen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
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RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference.