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Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge.

, , , , , , , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (2): 283-290 (February 2024)

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RRAM Computing-in-Memory Using Transient Charge Transferring for Low-Power and Small-Latency AI Edge Inference., , , , , , , , , and . APCCAS, page 497-500. IEEE, (2022)A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 58 (10): 2839-2850 (October 2023)Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge., , , , , , , , , and 5 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 32 (2): 283-290 (February 2024)Multicore Spiking Neuromorphic Chip in 180-nm With ReRAM Synapses and Digital Neurons., , , , , , , , , and 2 other author(s). IEEE J. Emerg. Sel. Topics Circuits Syst., 13 (4): 975-985 (December 2023)Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low Power Nonvolatile Computing-in-Memory Based on Resistive Memory., , , , , , and . ISCAS, page 1-4. IEEE, (2021)RRAM-based Analog-Weight Spiking Neural Network Accelerator with in-situ Learning for IoT Applications., , , , , and . ASICON, page 1-4. IEEE, (2021)Heterojunction Diode Shielded SiC Split-Gate Trench MOSFET With Optimized Reverse Recovery Characteristic and Low Switching Loss., and . IEEE Access, (2019)