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Disambiguation of "Reddy, Sudhakar M."

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On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression.

, and . VLSI Design, page 741-744. IEEE Computer Society, (2004)

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Sudhakar Peddireddi

Padhmanand Sudhakar

Edamakanti Chandrakanth Reddy

Malgi Prasad Reddy

Martin Reddy

 

Other publications of authors with the same name

Universal delay test sets for logic networks., , and . IEEE Trans. Very Large Scale Integr. Syst., 7 (2): 156-166 (1999)Correcting Unidirectional Errors with Nonpositive Hopfield Networks., , and . ICNN, page 2933-2938. IEEE, (1995)Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines., , , , and . DATE, page 1022-1027. IEEE, (2019)Selection of a fault model for fault diagnosis based on unique responses., and . DATE, page 994-999. IEEE, (2009)Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times., and . FTCS, page 52-59. IEEE Computer Society, (1991)EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits., and . FTCS, page 166-175. IEEE Computer Society, (1993)Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability., , , and . FTCS, page 280-287. IEEE Computer Society, (1992)On the design of robust testable CMOS combinational logic circuits., and . FTCS, page 220-225. IEEE Computer Society, (1988)A supervised machine learning application in volume diagnosis., , , , , , and . ETS, page 1-6. IEEE, (2019)Volume diagnosis data mining., , and . ETS, page 1-10. IEEE, (2017)