Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Low power SRAM design for 14 nm GAA Si-nanowire technology.

G. Kaushal, H. Jeong, S. Maheshwaram, S. Manhas, S. Dasgupta, and S. Jung. Microelectron. J., 46 (12): 1239-1247 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Seong-Jung Kim

Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

Other publications of authors with the same name

Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells.D. Ko, T. Oh, S. Lim, S. Kim, and S. Jung. IEEE Access, (2021)All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash.J. An, J. Chun, H. Park, and S. Jung. IEEE Access, (2021)A Novel Matchline Scheduling Method for Low-Power and Reliable Search Operation in Cross-Point-Array Nonvolatile Ternary CAM.H. Park, H. Ahn, and S. Jung. IEEE Trans. Very Large Scale Integr. Syst., 28 (12): 2650-2657 (2020)Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM.S. Choi, T. Na, J. Kim, J. Kim, S. Kang, and S. Jung. IEEE Trans. Very Large Scale Integr. Syst., 24 (9): 2851-2860 (2016)Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM.T. Na, J. Kim, S. Kang, and S. Jung. IEEE Trans. Very Large Scale Integr. Syst., 24 (9): 2993-2997 (2016)Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation.K. Kang, H. Jeong, Y. Yang, J. Park, K. Kim, and S. Jung. IEEE Trans. Very Large Scale Integr. Syst., 24 (4): 1342-1350 (2016)0.293-mm2 Fast Transient Response Hysteretic Quasi-V2 DC-DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35-µm CMOS.D. Jung, K. Kim, S. Jo, and S. Jung. IEEE J. Solid State Circuits, 53 (6): 1844-1855 (2018)Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM.J. Lee, H. Jeong, Y. Yang, J. Kim, and S. Jung. ISOCC, page 479-482. IEEE, (2012)A 0.67nJ/S time-domain temperature sensor for low power on-chip thermal management.Y. An, K. Ryu, D. Jung, S. Woo, and S. Jung. ICCE, page 572-573. IEEE, (2013)Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.K. Kim, S. Jung, P. Saxena, C. Liu, and S. Kang. DAC, page 732-737. ACM, (2001)

BibSonomy

Disambiguation of "Jung, Seong-Ook"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Low power SRAM design for 14 nm GAA Si-nanowire technology.

Please choose a person to relate this publication to

Seong-Jung Kim

Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Jung, Seong-Ook"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Low power SRAM design for 14 nm GAA Si-nanowire technology.

Please choose a person to relate this publication to

Seong-Jung Kim

Ki-Chang Seong

Seunghyeon Seong

Nak-Hyon Seong

Hong-Jae Seong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Low power SRAM design for 14 nm GAA Si-nanowire technology.