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Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications.

, , , , , and . Integr., (2018)

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Systematic test program generation for SoC testing using embedded processor., , , and . ISCAS (5), page 541-544. IEEE, (2003)High performance circuit techniques for dynamic OR gates., , and . ISCAS, IEEE, (2006)WL-VC SRAM: a low leakage memory circuit for deep sub-micron design., , and . ISCAS, IEEE, (2006)An Efficient Clocking Scheme for On-Chip Communications., , , and . APCCAS, page 119-122. IEEE, (2006)Low Power Combinational Multipliers using Data-driven Signal Gating., and . APCCAS, page 1430-1433. IEEE, (2006)BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (2): 302-306 (2009)OPLE: A Heuristic Custom Instruction Selection Algorithm Based on Partitioning and Local Exploration of Application Dataflow Graphs., , , and . ACM Trans. Embed. Comput. Syst., 14 (4): 72:1-72:23 (2015)All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (9): 1503-1508 (2016)A new merit function for custom instruction selection under an area budget constraint., , , , and . Des. Autom. Embed. Syst., 17 (1): 1-25 (2013)Distributing DNN training over IoT edge devices based on transfer learning., , , and . Neurocomputing, (2022)