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Systematic test program generation for SoC testing using embedded processor., , , и . ISCAS (5), стр. 541-544. IEEE, (2003)High performance circuit techniques for dynamic OR gates., , и . ISCAS, IEEE, (2006)WL-VC SRAM: a low leakage memory circuit for deep sub-micron design., , и . ISCAS, IEEE, (2006)An Efficient Clocking Scheme for On-Chip Communications., , , и . APCCAS, стр. 119-122. IEEE, (2006)Low Power Combinational Multipliers using Data-driven Signal Gating., и . APCCAS, стр. 1430-1433. IEEE, (2006)Simultaneous Reduction of Dynamic and Static Power in Scan Structures, , , , и . CoRR, (2007)ByZFAD: a low switching activity architecture for shift-and-add multipliers., , и . SBCCI, стр. 179-183. ACM, (2006)An efficent dynamic multicast routing protocol for distributing traffic in NOCs., , , , , , и . DATE, стр. 1064-1069. IEEE, (2009)An efficient network on-chip architecture based on isolating local and non-local communications., , , и . DATE, стр. 350-353. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Pipeline Event-driven No-race Charge recycling Logic (PENCL) for low power application., и . ICECS, стр. 220-223. IEEE, (2003)