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Pipeline Event-driven No-race Charge recycling Logic (PENCL) for low power application., and . ICECS, page 220-223. IEEE, (2003)BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (2): 302-306 (2009)An Efficient Clocking Scheme for On-Chip Communications., , , and . APCCAS, page 119-122. IEEE, (2006)Low Power Combinational Multipliers using Data-driven Signal Gating., and . APCCAS, page 1430-1433. IEEE, (2006)WL-VC SRAM: a low leakage memory circuit for deep sub-micron design., , and . ISCAS, IEEE, (2006)Systematic test program generation for SoC testing using embedded processor., , , and . ISCAS (5), page 541-544. IEEE, (2003)High performance circuit techniques for dynamic OR gates., , and . ISCAS, IEEE, (2006)Simultaneous Reduction of Dynamic and Static Power in Scan Structures, , , , and . CoRR, (2007)Sign bit reduction encoding for low power applications., , and . DAC, page 214-217. ACM, (2005)OPLE: A Heuristic Custom Instruction Selection Algorithm Based on Partitioning and Local Exploration of Application Dataflow Graphs., , , and . ACM Trans. Embed. Comput. Syst., 14 (4): 72:1-72:23 (2015)