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Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1352-1361 (2017)

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Sign bit reduction encoding for low power applications., , and . DAC, page 214-217. ACM, (2005)An efficient network on-chip architecture based on isolating local and non-local communications., , , and . DATE, page 350-353. EDA Consortium San Jose, CA, USA / ACM DL, (2013)An efficent dynamic multicast routing protocol for distributing traffic in NOCs., , , , , , and . DATE, page 1064-1069. IEEE, (2009)Pipeline Event-driven No-race Charge recycling Logic (PENCL) for low power application., and . ICECS, page 220-223. IEEE, (2003)Systematic test program generation for SoC testing using embedded processor., , , and . ISCAS (5), page 541-544. IEEE, (2003)High performance circuit techniques for dynamic OR gates., , and . ISCAS, IEEE, (2006)WL-VC SRAM: a low leakage memory circuit for deep sub-micron design., , and . ISCAS, IEEE, (2006)An Efficient Clocking Scheme for On-Chip Communications., , , and . APCCAS, page 119-122. IEEE, (2006)Low Power Combinational Multipliers using Data-driven Signal Gating., and . APCCAS, page 1430-1433. IEEE, (2006)Simultaneous Reduction of Dynamic and Static Power in Scan Structures, , , , and . CoRR, (2007)