%0 Conference Paper %1 conf/dac/JiangHPSCHLLCY20 %A Jiang, Hongwu %A Huang, Shanshi %A Peng, Xiaochen %A Su, Jian-Wei %A Chou, Yen-Chi %A Huang, Wei-Hsing %A Liu, Ta-Wei %A Liu, Ruhui %A Chang, Meng-Fan %A Yu, Shimeng %B DAC %D 2020 %I IEEE %K dblp %P 1-6 %T A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. %U http://dblp.uni-trier.de/db/conf/dac/dac2020.html#JiangHPSCHLLCY20 %@ 978-1-7281-1085-1

@inproceedings{conf/dac/JiangHPSCHLLCY20, added-at = {2023-03-21T00:00:00.000+0100}, author = {Jiang, Hongwu and Huang, Shanshi and Peng, Xiaochen and Su, Jian-Wei and Chou, Yen-Chi and Huang, Wei-Hsing and Liu, Ta-Wei and Liu, Ruhui and Chang, Meng-Fan and Yu, Shimeng}, biburl = {https://www.bibsonomy.org/bibtex/22925b155bf0064e1662a9f3684b6f106/dblp}, booktitle = {DAC}, crossref = {conf/dac/2020}, ee = {https://doi.org/10.1109/DAC18072.2020.9218524}, interhash = {277dfe08deaf463453449a48f0b561ea}, intrahash = {2925b155bf0064e1662a9f3684b6f106}, isbn = {978-1-7281-1085-1}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2024-04-10T06:55:34.000+0200}, title = {A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac2020.html#JiangHPSCHLLCY20}, year = 2020 }