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Disambiguation of "Jiang, Hongwu"

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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.

, , , , , , , , , and . DAC, page 1-6. IEEE, (2020)

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Hongwu Zhang

Ping Jiang

Jiang Yi

Xin Jiang

Kaiyun Jiang

 

Other publications of authors with the same name

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training., , , , and . CoRR, (2020)DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (11): 2306-2319 (2021)A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References., , , , and . IEEE J. Solid State Circuits, 57 (9): 2868-2877 (2022)NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark., , , , and . Frontiers Artif. Intell., (2021)A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling., , , and . ESSCIRC, page 101-104. IEEE, (2022)Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 57 (2): 609-624 (2022)ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (1): 353-363 (January 2023)Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators., , and . ACM Trans. Design Autom. Electr. Syst., 28 (3): 34:1-34:23 (2023)Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices., , , , and . ACM Trans. Design Autom. Electr. Syst., 27 (4): 37:1-37:19 (2022)Architecture and Circuit Design Optimization for Compute-In-Memory.. Georgia Institute of Technology, Atlanta, GA, USA, (2023)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/70137).