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A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training.

, , , , , , , , , и . DAC, стр. 1-6. IEEE, (2020)

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Feiqing Huang

Zhida Huang

Ying Huang

Haowei Huang

Haishi Huang

 

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Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 29 (12): 2027-2039 (2021)Mitigating Adversarial Attack for Compute-in-Memory Accelerator Utilizing On-chip Finetune., , и . NVMSA, стр. 1-6. IEEE, (2021)A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training., , , , , , , , , и . DAC, стр. 1-6. IEEE, (2020)Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects., , , и . CICC, стр. 1-4. IEEE, (2020)DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training., , , , и . CoRR, (2020)DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (11): 2306-2319 (2021)A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References., , , , и . IEEE J. Solid State Circuits, 57 (9): 2868-2877 (2022)A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference., , , , и . ACM Trans. Design Autom. Electr. Syst., 26 (6): 45:1-45:18 (2021)Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators., , , , , и . IEEE Des. Test, 39 (2): 48-55 (2022)A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References., , , , и . ESSCIRC, стр. 79-82. IEEE, (2021)