%0 Journal Article %1 journals/jssc/LeeASZKVCFGCMOL22 %A Lee, Sae Kyu %A Agrawal, Ankur %A Silberman, Joel %A Ziegler, Matthew M. %A Kang, Mingu %A Venkataramani, Swagath %A Cao, Nianzheng %A Fleischer, Bruce M. %A Guillorn, Michael %A Cohen, Matthew %A Mueller, Silvia M. %A Oh, Jinwook %A Lutz, Martin %A Jung, Jinwook %A Koswatta, Siyu %A Zhou, Ching %A Zalani, Vidhi %A Kar, Monodeep %A Bonanno, James %A Casatuta, Robert %A Chen, Chia-Yu %A Choi, Jungwook %A Haynie, Howard %A Herbert, Alyssa %A Jain, Radhika %A Kim, Kyu-Hyoun %A Li, Yulong %A Ren, Zhibin %A Rider, Scot %A Schaal, Marcel %A Schelm, Kerstin %A Scheuermann, Michael %A Sun, Xiao %A Tran, Hung %A Wang, Naigang %A Wang, Wei %A Zhang, Xin %A Shah, Vinay %A Curran, Brian W. %A Srinivasan, Vijayalakshmi %A Lu, Pong-Fei %A Shukla, Sunil %A Gopalakrishnan, Kailash %A Chang, Leland %D 2022 %J IEEE J. Solid State Circuits %K dblp %N 1 %P 182-197 %T A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. %U http://dblp.uni-trier.de/db/journals/jssc/jssc57.html#LeeASZKVCFGCMOL22 %V 57

@article{journals/jssc/LeeASZKVCFGCMOL22, added-at = {2023-08-19T00:00:00.000+0200}, author = {Lee, Sae Kyu and Agrawal, Ankur and Silberman, Joel and Ziegler, Matthew M. and Kang, Mingu and Venkataramani, Swagath and Cao, Nianzheng and Fleischer, Bruce M. and Guillorn, Michael and Cohen, Matthew and Mueller, Silvia M. and Oh, Jinwook and Lutz, Martin and Jung, Jinwook and Koswatta, Siyu and Zhou, Ching and Zalani, Vidhi and Kar, Monodeep and Bonanno, James and Casatuta, Robert and Chen, Chia-Yu and Choi, Jungwook and Haynie, Howard and Herbert, Alyssa and Jain, Radhika and Kim, Kyu-Hyoun and Li, Yulong and Ren, Zhibin and Rider, Scot and Schaal, Marcel and Schelm, Kerstin and Scheuermann, Michael and Sun, Xiao and Tran, Hung and Wang, Naigang and Wang, Wei and Zhang, Xin and Shah, Vinay and Curran, Brian W. and Srinivasan, Vijayalakshmi and Lu, Pong-Fei and Shukla, Sunil and Gopalakrishnan, Kailash and Chang, Leland}, biburl = {https://www.bibsonomy.org/bibtex/21cc1d923053d964abab904bfbc9fb24a/dblp}, ee = {https://doi.org/10.1109/JSSC.2021.3120113}, interhash = {740228677e16234d5bd0c470d159907c}, intrahash = {1cc1d923053d964abab904bfbc9fb24a}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 1, pages = {182-197}, timestamp = {2024-04-08T10:44:42.000+0200}, title = {A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc57.html#LeeASZKVCFGCMOL22}, volume = 57, year = 2022 }