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A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.

S. Lee, A. Agrawal, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen, S. Mueller, J. Oh, M. Lutz, J. Jung, S. Koswatta, C. Zhou, V. Zalani, M. Kar, J. Bonanno, R. Casatuta, C. Chen, J. Choi, H. Haynie, A. Herbert, R. Jain, K. Kim, Y. Li, Z. Ren, S. Rider, M. Schaal, K. Schelm, M. Scheuermann, X. Sun, H. Tran, N. Wang, W. Wang, X. Zhang, V. Shah, B. Curran, V. Srinivasan, P. Lu, S. Shukla, K. Gopalakrishnan, and L. Chang. IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)

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Yang Cao

Jingjing Cao

Yude Cao

Hong Cao

Weixun Cao

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Efficient AI System Design With Cross-Layer Approximate Computing.S. Venkataramani, X. Sun, N. Wang, C. Chen, J. Choi, M. Kang, A. Agarwal, J. Oh, S. Jain, T. Babinsky and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors.P. Lu, N. Cao, L. Sigal, P. Woltgens, R. Robertazzi, and D. Heidel. ISLPED, page 85-88. ACM, (2006)Across the Stack Opportunities for Deep Learning Acceleration.V. Srinivasan, B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.J. Barth, D. Plass, E. Nelson, C. Hwang, G. Fredeman, M. Sperling, A. Mathews, T. Kirihata, W. Reohr, K. Nair and 1 other author(s). IEEE J. Solid State Circuits, 46 (1): 64-75 (2011)A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.A. Agrawal, S. Lee, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). ISSCC, page 144-146. IEEE, (2021)A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache.J. Barth, D. Plass, E. Nelson, C. Hwang, G. Fredeman, M. Sperling, A. Mathews, W. Reohr, K. Nair, and N. Cao. ISSCC, page 342-343. IEEE, (2010)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.S. Lee, A. Agrawal, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.S. Venkataramani, V. Srinivasan, W. Wang, S. Sen, J. Zhang, A. Agrawal, M. Kar, S. Jain, A. Mannari, H. Tran and 44 other author(s). ISCA, page 153-166. IEEE, (2021)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.J. Oh, S. Lee, M. Kang, M. Ziegler, J. Silberman, A. Agrawal, S. Venkataramani, B. Fleischer, M. Guillorn, J. Choi and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)

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Disambiguation of "Cao, Nianzheng"

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A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.

Please choose a person to relate this publication to

Yang Cao

Jingjing Cao

Yude Cao

Hong Cao

Weixun Cao

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cao, Nianzheng"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.

Please choose a person to relate this publication to

Yang Cao

Jingjing Cao

Yude Cao

Hong Cao

Weixun Cao

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
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A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.