%0 Conference Paper %1 conf/tase/Wang0TDXY23 %A Wang, Wu %A Zhang, Nan %A Tian, Cong %A Duan, Zhenhua %A Xu, Zhijie %A Yu, Chaofeng %B TASE %D 2023 %E David, Cristina %E Sun, Meng %I Springer %K dblp %P 146-163 %T Verifying Chips Design at RTL Level. %U http://dblp.uni-trier.de/db/conf/tase/tase2023.html#Wang0TDXY23 %V 13931 %@ 978-3-031-35257-7

@inproceedings{conf/tase/Wang0TDXY23, added-at = {2023-06-30T00:00:00.000+0200}, author = {Wang, Wu and Zhang, Nan and Tian, Cong and Duan, Zhenhua and Xu, Zhijie and Yu, Chaofeng}, biburl = {https://www.bibsonomy.org/bibtex/2b4600c2249b44e16b637bb0c0b642300/dblp}, booktitle = {TASE}, crossref = {conf/tase/2023}, editor = {David, Cristina and Sun, Meng}, ee = {https://doi.org/10.1007/978-3-031-35257-7_9}, interhash = {e46d2fa351c2205c502e806462a08dea}, intrahash = {b4600c2249b44e16b637bb0c0b642300}, isbn = {978-3-031-35257-7}, keywords = {dblp}, pages = {146-163}, publisher = {Springer}, series = {Lecture Notes in Computer Science}, timestamp = {2024-04-10T01:48:24.000+0200}, title = {Verifying Chips Design at RTL Level.}, url = {http://dblp.uni-trier.de/db/conf/tase/tase2023.html#Wang0TDXY23}, volume = 13931, year = 2023 }