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Verifying Chips Design at RTL Level.

, , , , , and . TASE, volume 13931 of Lecture Notes in Computer Science, page 146-163. Springer, (2023)

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Wavelet-Based Time-Reassigned Synchroextracting Transform With Application to Fault Diagnosis of Flexible Thin-Wall Bearing., , and . IEEE Trans. Instrum. Meas., (2023)An Approach to Agent Path Planning Under Temporal Logic Constraints., , , and . COCOON (2), volume 14423 of Lecture Notes in Computer Science, page 82-93. Springer, (2023)A proof system for unified temporal logic., , , and . Theor. Comput. Sci., (March 2023)Verifying Chips Design at RTL Level., , , , , and . TASE, volume 13931 of Lecture Notes in Computer Science, page 146-163. Springer, (2023)