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Disambiguation of "Pfleiderer, Hans-Jörg"

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A VLSI architecture for a Run-time Multi-precision Reconfigurable Booth Multiplier.

, , , and . ICECS, page 975-978. IEEE, (2007)

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Hans-Jörg Pfleiderer

Jörg Pfleiderer

Jörg Pfleiderer

Hans Pfleiderer

Hans Pfleiderer

 

Other publications of authors with the same name

3D Chip Stack Technology Using Through-Chip Interconnects., , , , , , , , and . IEEE Des. Test Comput., 22 (6): 512-518 (2005)A function-independent self-test for large programmable logic arrays., and . Integr., 1 (1): 71-80 (1983)Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures., and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 69-78. Springer, (2004)A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 938-942. Springer, (2004)Modelling the glucose metabolism with backpropagation through time trained Elman nets., , , , and . NNSP, page 789-798. IEEE, (2003)Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations., and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 496-503. Springer, (2006)Symbolic pole/zero calculation using SANTAFE., , and . IEEE J. Solid State Circuits, 30 (7): 752-761 (July 1995)An ECL to CMOS level converter with complementary bipolar output stage., and . IEEE J. Solid State Circuits, 30 (7): 781-787 (July 1995)Design and Implementation of Discrete Event Control Systems: A Petri Net Based Hardware Approach., , , and . Discrete Event Dynamic Systems, 12 (3): 287-309 (2002)Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA., and . DELTA, page 474-477. IEEE Computer Society, (2008)